View MAX19517_4677723.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX19517 dual-channel, analog-to-digital converter (adc) provides 10-bit resolution and a maximum sam- ple rate of 130msps. the MAX19517 analog input accepts a wide 0.4v to 1.4v input common-mode voltage range, allowing dc- coupled inputs for a wide range of rf, if, and base- band front-end components. the MAX19517 provides excellent dynamic performance from baseband to high input frequencies beyond 400mhz, making the device ideal for zero-intermediate frequency (zif) and high- intermediate frequency (if) sampling applications. the typical signal-to-noise ratio (snr) performance is 59.8dbfs and typical spurious-free dynamic range (sfdr) is 82dbc at f in = 70mhz and f clk = 130mhz. the MAX19517 operates from a 1.8v supply. additionally, an integrated, self-sensing voltage regula- tor allows operation from a 2.5v to 3.3v supply (avdd). the digital output drivers operate on an independent supply voltage (ovdd) over the 1.8v to 3.5v range. the analog power consumption is only 74mw per chan- nel at v avdd = 1.8v. in addition to low operating power, the MAX19517 consumes only 1mw in power- down mode and 21mw in standby mode. various adjustments and feature selections are avail- able through programmable registers that are accessed through the 3-wire serial-port interface. alternatively, the serial-port interface can be disabled, with the three pins available to select output mode, data format, and clock-divider mode. data outputs are available through a dual parallel cmos-compatible out- put data bus that can also be configured as a single multiplexed parallel cmos bus. the MAX19517 is available in a small 7mm x 7mm 48- pin thin qfn package and is specified over the -40? to +85? extended temperature range. refer to the max19505, max19506, and max19507 data sheets for pin- and feature-compatible 8-bit, 65msps, 100msps, and 130msps versions, respectively. refer to the max19515 and max19516 data sheets for pin- and feature-compatible 10-bit, 65msps and 100msps versions, respectively. applications if and baseband communications, including cellular base stations and point-to-point microwave receivers ultrasound and medical imaging portable instrumentation and low-power data acquisition digital set-top boxes features very-low-power operation (74mw/channel at 130msps) 1.8v or 2.5v to 3.3v analog supply excellent dynamic performance 59.8dbfs snr at 70mhz 82dbc sfdr at 70mhz user-programmable adjustments and feature selection through an spi interface selectable data bus (dual cmos or single multiplexed cmos) dclk output and programmable data output timing simplifies high-speed digital interface very wide input common-mode voltage range (0.4v to 1.4v) very high analog input bandwidth (> 850mhz) single-ended or differential analog inputs single-ended or differential clock input divide-by-one (div1), divide-by-two (div2), and divide-by-four (div4) clock modes two? complement, gray code, and offset binary output data format out-of-range indicator (dor) cmos output internal termination options (programmable) reversible bit order (programmable) data output test patterns small 7mm x 7mm 48-pin thin qfn package with exposed pad MAX19517 dual-channel, 10-bit, 130msps adc ________________________________________________________________ maxim integrated products 1 ordering information 19-4227; rev 1; 10/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX19517etm+ -40? to +85? 48 tqfn-ep* + denotes a lead-free/rohs-compliant package. * ep = exposed pad. pin configuration appears at end of data sheet. spi is a trademark of motorola, inc.
MAX19517 dual-channel, 10-bit, 130msps adc 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 ? , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ovdd, avdd to gnd............................................-0.3v to +3.6v cma, cmb, refio, ina+, ina-, inb+, inb- to gnd ......................................................-0.3v to +2.1v clk+, clk-, sync, spen , cs , sclk, sdin to gnd ..........-0.3v to the lower of (v avdd + 0.3v) and +3.6v dclka, dclkb, d9a?0a, d9b?0b, dora, dorb to gnd..........-0.3v to the lower of (v ovdd + 0.3v) and +3.6v continuous power dissipation (t a = +70?) 48-pin thin qfn, 7mm x 7mm x 0.8mm (derate 40mw/? above +70?).............................................................3200mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity inl f in = 3mhz -0.8 ?.25 +0.8 lsb differential nonlinearity dnl f in = 3mhz -0.7 ?.2 +0.7 lsb offset error oe internal reference -0.4 ?.1 +0.4 %fs gain error ge external reference = 1.25v -1.5 ?.3 +1.5 %fs analog inputs (ina+, ina-, inb+, inb-) (figure 3) differential input-voltage range v diff differential or single-ended inputs 1.5 v p-p common-mode input-voltage range v cm (note 2) 0.4 1.4 v fixed resistance > 100 input resistance r in differential input resistance, common mode connected to inputs 4 k ? input current i in switched capacitance input current, each input 74 ? c par fixed capacitance to ground, each input 0.7 input capacitance c sample switched capacitance, each input 1.2 pf conversion rate maximum clock frequency f clk 130 mhz minimum clock frequency f clk 65 mhz data latency figures 9, 10 9 cycles
MAX19517 dual-channel, 10-bit, 130msps adc _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units dynamic performance small-signal noise floor ssnf f in = 70mhz, < -35dbfs -60.1 dbfs f in = 3mhz 59.9 f in = 70mhz 58.6 59.8 signal-to-noise ratio snr f in = 175mhz 59.5 dbfs f in = 3mhz 59.4 f in = 70mhz 58.0 59.4 signal-to-noise plus distortion ratio sinad f in = 175mhz 59.3 db f in = 3mhz 82 f in = 70mhz 70.1 81 spurious-free dynamic range (2nd and 3rd harmonic) sfdr1 f in = 175mhz 78 dbc f in = 3mhz 82 f in = 70mhz 74 82 spurious-free dynamic range (4th and higher harmonics) sfdr2 f in = 175mhz 82 dbc f in = 3mhz -82 f in = 70mhz -81 -70.1 second harmonic hd2 f in = 175mhz -78 dbc f in = 3mhz -86 f in = 70mhz -86 -71.5 third harmonic hd3 f in = 175mhz -80 dbc f in = 3mhz -79 f in = 70mhz -78 -68.8 total harmonic distortion thd f in = 175mhz -76 dbc f in = 70mhz ?1.5mhz, -7dbfs -90 third-order intermodulation im3 f in = 175mhz ?2.5mhz, -7dbfs -80 dbc full-power bandwidth fpbw 850 mhz aperture delay t ad 850 ps aperture jitter t aj 0.3 ps rms overdrive recovery time ?0% beyond full scale 1 cycles electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 ? , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1)
MAX19517 dual-channel, 10-bit, 130msps adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 ? , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units interchannel characteristics f ina or f inb = 70mhz at -1dbfs 95 crosstalk f ina or f inb = 175mhz at -1dbfs 85 dbc gain match f in = 70mhz ?.05 db offset match f in = 70mhz ?.15 %fsr phase match f in = 70mhz ?.5 d eg r ees analog outputs (cma, cmb) cma, cmb output voltage v com default programmable setting 0.85 0.9 0.95 v internal reference refio output voltage v refout 1.23 1.25 1.27 v refio temperature coefficient tc ref < ?0 ppm/? external reference refio input-voltage range v refin 1.25 +5/ -10% v refio input resistance r refin 10 ?0% k ? clock inputs (clk+, clk-)?ifferential mode differential clock input voltage 0.4 to 2.0 v p-p self-biased 1.2 differential input common-mode voltage dc-coupled clock signal 1.0 to 1.4 v differential, default 10 k ? differential, internal termination selected 100 ? input resistance r clk common mode 9 k ? input capacitance c clk to ground, each input 3 pf clock inputs (clk+, clk-)?ingle-ended mode (v clk- < 0.1v) single-ended mode selection threshold (v clk- ) 0.1 v allowable logic swing (v clk+ ) 0 - v avdd v single-ended clock input high threshold (v clk+ ) 1.5 v single-ended clock input low threshold (v clk+ ) 0.3 v v clk+ = v avdd = 1.8v or 3.3v +0.5 input leakage (clk+) v clk+ = 0 -0.5 ? input leakage (clk-) v clk- = 0 -150 -50 ? input capacitance (clk+) 3pf
MAX19517 dual-channel, 10-bit, 130msps adc _______________________________________________________________________________________ 5 electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 ? , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units clock inputs (sync) allowable logic swing 0 - v avdd v sync clock input high threshold 1.5 v sync clock input low threshold 0.3 v v sync = v avdd = 1.8v or 3.3v +0.5 input leakage v sync = 0 -0.5 ? input capacitance 4.5 pf digital inputs (shdn, spen ) allowable logic swing 0 - v avdd v input high threshold 1.5 v input low threshold 0.3 v v shdn /v spen = v avdd = 1.8v or 3.3v +0.5 input leakage v shdn /v spen = 0 -0.5 ? input capacitance c din 3pf serial-port inputs (sclk, sdin, cs , where spen = 0v)?erial-port control mode allowable logic swing 0 - v avdd v input high threshold 1.5 v input low threshold 0.3 v v sclk /v sdin /v cs = v avdd = 1.8v or 3.3v +0.5 input leakage v sclk /v sdin /v cs = 0 -0.5 ? input capacitance c din 3pf serial-port inputs (sclk, sdin, cs , where spen = v avdd )?arallel control mode (figure 5) v sclk /v sdin /v cs = v avdd = 1.8v 7 12 17 input pullup current v sclk /v sdin /v cs = v avdd = 3.3v 16 21 26 ? v sclk /v sdin /v cs = 0, v avdd = 1.8v -65 -50 -35 input pulldown current v sclk /v sdin /v cs = 0, v avdd = 3.3v -105 -90 -75 ? i = 0v, v avdd = 1.8v 1.35 1.45 1.55 open-circuit voltage v oc i = 0v, v avdd = 3.3v 2.58 2.68 2.78 v digital outputs (75 ? , d0?9 (a and b channel), dclka, dclkb, dora, dorb) output-voltage low v ol i sink = 200? 0.2 v output-voltage high v oh i source = 200? v ovdd - 0.2 v v ovdd applied +0.5 three-state leakage current i leak gnd applied -0.5 ?
MAX19517 dual-channel, 10-bit, 130msps adc 6 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 ? , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units power-management characteristics wake-up time from shutdown t wake internal reference, c refio = 0.1? (10 )5ms wake-up time from standby t wake internal reference 15 s serial-port interface timing (note 2) (figure 7) sclk period t sclk 50 ns sclk to cs setup time t css 10 ns sclk to cs hold time t csh 10 ns sdin to sclk setup time t sds serial-data write 10 ns sdin to sclk hold time t sdh serial-data write 0 ns sclk to sdin output data delay t sdd serial-data read 10 ns timing characteristics?ual bus parallel mode (figure 9), (default timing see table 5) clock pulse-width high t ch 3.85 ns clock pulse-width low t cl 3.85 ns clock duty cycle t ch /t clk 30 to 70 % c l = 10pf, v ovdd = 1.8v (note 2) 9.7 12.2 14.7 data delay after rising edge of clk+ t dd c l = 10pf, v ovdd = 3.3v 11.0 ns data to dclk setup time t setup c l = 10pf, v ovdd = 1.8v (note 2) 5.9 6.7 ns data to dclk hold time t hold c l = 10pf, v ovdd = 1.8v (note 2) 0.5 0.9 ns timing characteristics?ultiplexed bus parallel mode (figure 10), (default timing see table 5) clock pulse-width high t ch 3.85 ns clock pulse-width low t cl 3.85 ns clock duty cycle t ch /t clk 30 to 70 % c l = 10pf, v ovdd = 1.8v (note 2) 6.0 8.3 11.0 data delay after rising edge of clk+ t dd c l = 10pf, v ovdd = 3.3v 7.6 ns data to dclk setup time t setup c l = 10pf, v ovdd = 1.8v (note 2) 0.7 2.4 ns data to dclk hold time t hold c l = 10pf, v ovdd = 1.8v (note 2) 0.4 1.5 ns dclk duty cycle t dch /t clk c l = 10pf, v ovdd = 1.8v (note 2) 30 50 63 % mux data duty cycle t cha /t clk c l = 10pf, v ovdd = 1.8v (note 2) 38 50 75 % timing characteristics?ynchronization (figure 12) setup time for valid clock edge t suv edge mode (note 2) 0.7 ns hold-off time for invalid clock edge t ho edge mode (note 2) 0.5 ns minimum synchronization pulse width relative to input clock period 2 cycles
MAX19517 dual-channel, 10-bit, 130msps adc _______________________________________________________________________________________ 7 electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 ? , t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units power requirements low-level v avdd 1.7 1.9 analog supply voltage v avdd high-level v avdd (regulator mode, invoked automatically) 2.3 3.5 v digital output supply voltage v ovdd 1.7 3.5 v dual channel 82 95 single channel active 48 standby mode 11.5 15 power-down mode 0.65 0.9 analog supply current i avdd power-down mode, v avdd = 3.3v 1.6 ma dual channel 148 171 dual channel, v avdd = 3.3v 271 single channel active 86 standby mode 21 27 power-down mode 1.2 1.6 analog power dissipation p da power-down mode, v avdd = 3.3v 2.9 mw dual-channel mode, c l = 10pf 26 digital output supply current i ovdd power-down mode < 0.1 ma note 1: specifications +25? guaranteed by production test, specifications < +25? guaranteed by design and characterization. note 2: guaranteed by design and characterization.
175mhz two-tone imd plot frequency (mhz) amplitude (dbfs) MAX19517 toc06 0 102030405060 -120 -100 -80 -60 -40 -20 0 f in1 = 173.60244mhz f in2 = 177.66891mhz 70mhz two-tone imd plot frequency (mhz) amplitude (dbfs) MAX19517 toc05 0 102030405060 -120 -100 -80 -60 -40 -20 0 f in1 = 71.484527mhz f in2 = 68.612213mhz 175mhz input fft plot frequency (mhz) amplitude (dbfs) MAX19517 toc04 0 102030405060 -120 -100 -80 -60 -40 -20 0 f in = 175.105056mhz a in = -0.479dbfs snr = 59.060db sinad = 58.978db thd = -76.283dbc sfdr1 = 80.374dbc sfdr2 = 80.246dbc 70mhz input fft plot frequency (mhz) amplitude (dbfs) MAX19517 toc03 0 102030405060 -120 -100 -80 -60 -40 -20 0 f in = 70.1088714mhz a in = -0.496dbfs snr = 59.421db sinad = 58.384db thd = -80.097dbc sfdr1 = 87.501dbc sfdr2 = 83.292dbc 3mhz single-ended input fft plot frequency (mhz) amplitude (dbfs) MAX19517 toc02 0 102030405060 -120 -100 -80 -60 -40 -20 0 f in = 2.99827576mhz a in = -0.471dbfs snr = 58.952db sinad = 58.470db thd = -68.261dbc sfdr1 = 68.631dbc sfdr2 = 86.050dbc MAX19517 dual-channel, 10-bit, 130msps adc 8 _______________________________________________________________________________________ typical operating characteristics (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 ? , t a = +25?, unless otherwise noted.) 3mhz input fft plot frequency (mhz) amplitude (dbfs) MAX19517 toc01 0 102030405060 -120 -100 -80 -60 -40 -20 0 f in = 2.99827576mhz a in = -0.545dbfs snr = 59.525db sinad = 59.472db thd = -78.638dbc sfdr1 = 89.933dbc sfdr2 = 80.307dbc integral nonlinearity vs. digital output code digital output code inl (lsb) MAX19517 toc07 0 256 512 768 1024 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 differential nonlinearity vs. digital output code digital output code dnl (lsb) MAX19517 toc08 0 256 512 768 1024 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 performance vs. input frequency MAX19517 toc09 input frequency (mhz) performance (dbfs) 300 200 100 55 60 65 70 75 80 85 90 50 0400 250 150 50 350 sfdr2 sfdr1 -thd sinad snr
analog supply current vs. supply voltage MAX19517 toc18 supply voltage (v) analog supply current (ma) 1.90 1.85 1.80 1.75 1.70 78 80 82 84 86 88 90 76 1.65 1.95 performance vs. analog input amplitude MAX19517 toc11 analog input amplitude (dbfs) performance (dbfs) -10 -20 -30 -40 -50 60 70 80 90 100 110 50 -60 0 sfdr2 sfdr1 -thd sinad snr single-ended performance vs. input frequency MAX19517 toc10 input frequency (mhz) single-ended performance (dbfs) 60 50 10 20 30 40 55 60 65 70 75 80 85 90 50 070 sfdr2 sfdr1 -thd sinad snr typical operating characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 ? , t a = +25?, unless otherwise noted.) MAX19517 dual-channel, 10-bit, 130msps adc _______________________________________________________________________________________ 9 performance vs. sampling frequency MAX19517 toc12 sampling frequency (msps) performance (dbfs) 130 135 120 125 100 105 110 115 55 60 65 70 80 75 85 90 50 90 95 140 sfdr2 sfdr1 -thd sinad snr performance vs. common-mode voltage MAX19517 toc13 common-mode voltage (v) performance (dbfs) 1.35 1.15 0.95 0.75 0.55 55 60 65 70 75 80 85 90 95 50 0.35 sfdr2 sfdr1 -thd sinad snr performance vs. analog supply voltage MAX19517 toc14 analog supply voltage performance (dbfs) 1.90 1.85 1.70 1.75 1.80 55 60 65 70 75 80 85 90 50 1.65 1.95 sfdr2 sfdr1 -thd sinad snr performance vs. analog supply voltage MAX19517 toc15 analog supply voltage (v) performance (dbfs) 3.35 3.15 2.55 2.75 2.95 55 60 65 70 75 80 85 90 50 2.35 3.55 sfdr2 sfdr1 -thd sinad snr analog supply current vs. sampling frequency MAX19517 toc16 sampling frequency (mhz) analog supply current (ma) 130 120 110 100 135 125 115 105 65 70 75 80 85 90 60 90 95 140 analog supply current vs. temperature MAX19517 toc17 temperature ( c) analog supply current (ma) 80 60 40 20 0 -20 75 80 85 90 95 70 -40
10 ______________________________________________________________________________________ typical operating characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 ? , t a = +25?, unless otherwise noted.) analog supply current vs. supply voltage MAX19517 toc19 supply voltage (v) analog supply current (ma) 3.5 3.3 3.1 2.9 2.7 2.5 78 80 82 84 86 88 90 76 2.3 MAX19517 dual-channel, 10-bit, 130msps adc digital supply current vs. sampling frequency MAX19517 toc20 sampling frequency (msps) digital supply current (ma) 120 110 100 5 10 15 20 25 30 35 0 90 125 115 105 95 130 ovdd = 1.8v digital supply current vs. sampling frequency MAX19517 toc21 sampling frequency (msps) digital supply current (ma) 120 110 100 10 20 30 40 50 60 70 80 0 90 125 115 105 95 130 ovdd = 3.6v digital supply current vs. temperature maax19517 toc22 temperature ( c) digital supply current (ma) 80 60 40 20 0 -20 25 30 35 40 45 50 20 -40 ovdd = 3.6v ovdd = 1.8v digital supply current vs. supply voltage supply voltage (v) supply current (ma) MAX19517 toc23 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 0 5 10 15 20 25 30 35 40 45 50 dual bus digital supply current vs. supply voltage supply voltage (v) supply current (ma) MAX19517 toc24 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 0 5 10 15 20 25 30 35 40 45 50 multiplexed bus performance vs. clock duty cycle MAX19517 toc25 clock duty cycle (%) performance (dbfs) 60 55 35 40 45 50 60 65 70 75 80 85 90 95 55 30 65 sfdr2 sfdr1 -thd sinad snr performance vs. temperature MAX19517 toc26 temperature ( c) performance (dbfs) 80 60 -20 0 20 40 55 60 65 70 75 80 85 90 50 -40 sfdr2 sfdr1 -thd sinad snr gain error vs. temperature MAX19517 toc27 temperature ( c) gain error (%) 80 60 20 40 0 -20 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -0.05 -40
typical operating characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 130mhz, a in = -0.5dbfs, data output termina- tion = 50 ? , t a = +25?, unless otherwise noted.) common-mode voltage vs. temperature MAX19517 toc30 temperature ( c) common-mode voltage (v) 80 60 -20 0 20 40 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 -40 v cm = 1.35v v cm = 1.2v v cm = 1.05v v cm = 0.9v v cm = 0.75v v cm = 0.6v v cm = 0.45v offset error vs. temperature MAX19517 toc28 temperature ( c) offset error (mv) 80 60 20 40 0 -20 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 -0.7 -40 MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 11 reference voltage vs. temperature MAX19517 toc29 temperature ( c) reference voltage (v) 80 60 40 20 0 -20 1.2453 1.2474 1.2495 1.2516 1.2432 -40 gain error vs. supply voltage supply voltage (v) gain error (%) MAX19517 toc31 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 regulator mode input current vs. common-mode voltage common-mode voltage (v) input current ( a) MAX19517 toc32 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 40 50 60 70 80 90 100 110
MAX19517 dual-channel, 10-bit, 130msps adc 12 ______________________________________________________________________________________ pin description pin name function 1, 12, 13, 48 avdd analog supply voltage. bypass each avdd input pair (1, 48) and (12, 13) to gnd with 0.1?. 2 cma channel a common-mode input-voltage reference 3 ina+ channel a positive analog input 4 ina- channel a negative analog input 5 spen active-low spi enable. drive high to enable parallel programming mode. 6 refio reference input/output. to use internal reference, bypass to gnd with a > 0.1? capacitor. see the reference input/output (refio) section for external reference adjustment. 7 shdn active-high power-down. if spen is high (parallel programming mode), a register reset is initiated on the falling edge of shdn. 8 i.c. internally connected. leave unconnected. 9 inb+ channel b positive analog input 10 inb- channel b negative analog input 11 cmb channel b common-mode input-voltage reference 14 sync clock-divider mode synchronization input 15 clk+ clock positive input 16 clk- clock negative input. if clk- is connected to ground, clk+ is a single-ended logic-level clock input. otherwise, clk+/clk- are self-biased differential clock inputs. 17, 18 gnd ground. connect all ground inputs and ep (exposed pad) together. 19 dorb channel b data over range 20 dclkb channel b data clock 21 d0b channel b three-state digital output, bit 0 (lsb) 22 d1b channel b three-state digital output, bit 1 23 d2b channel b three-state digital output, bit 2 24 d3b channel b three-state digital output, bit 3 25, 36 ovdd digital supply voltage. bypass each ovdd input to gnd with 0.1? capacitor. 26 d4b channel b three-state digital output, bit 4 27 d5b channel b three-state digital output, bit 5 28 d6b channel b three-state digital output, bit 6 29 d7b channel b three-state digital output, bit 7 30 d8b channel b three-state digital output, bit 8 31 d9b channel b three-state digital output, bit 9 (msb) 32 d0a channel a three-state digital output, bit 0 (lsb) 33 d1a channel a three-state digital output, bit 1 34 d2a channel a three-state digital output, bit 2 35 d3a channel a three-state digital output, bit 3 37 d4a channel a three-state digital output, bit 4 38 d5a channel a three-state digital output, bit 5 39 d6a channel a three-state digital output, bit 6
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 13 detailed description the MAX19517 uses a 10-stage, fully differential, pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consump- tion. samples taken at the inputs move progressively through the pipeline stages every half clock cycle. from input to output the total latency is 9 clock cycles. each pipeline converter stage converts its input voltage to a digital output code. at every stage, except the last, the error between the input voltage and the digital out- put code is multiplied and passed on to the next pipeline stage. digital error correction compensates for adc comparator offsets in each pipeline stage and ensures no missing codes. figure 2 shows the MAX19517 functional diagram. analog inputs and common-mode reference apply the analog input signal to the analog inputs (ina+/ina- or inb+/inb-), which are connected to the input sampling switch (figure 3). when the input sam- pling switch is closed, the input signal is applied to the sampling capacitors through the input switch resistance. the input signal is sampled at the instant the input switch opens. the pipeline adc processes the sampled voltage and the digital output result is available 9 clock cycles later. before the input switch is closed to begin the next sampling cycle, the sampling capacitors are reset to the input common-mode potential. common-mode bias can be provided externally or internally through 2k ? resistors. in dc-coupled applica- tions, the signal source provides the external bias and the bias current. in ac-coupled applications, the input current is supplied by the common-mode input voltage. for example, the input current can be supplied through the center tap of a transformer secondary winding. alternatively, program the appropriate internal register through the serial-port interface to supply the input dc current through internal 2k ? resistors (figure 3). when the input current is supplied through the internal resis- tors, the input common-mode potential is reduced by the voltage drop across the resistors. the common- mode input reference voltage can be adjusted through programmable register settings from 0.45v to 1.35v in 0.15v increments. the default setting is 0.90v. use this feature to provide a common-mode output reference to a dc-coupled driving circuit. pin description (continued) pin name function 40 d7a channel a three-state digital output, bit 7 41 d8a channel a three-state digital output, bit 8 42 d9a channel a three-state digital output, bit 9 (msb) 43 dora channel a data over range 44 dclka channel a data clock 45 sdin/format spi data input/format. serial-data input when spen is low. output data format when spen is high. 46 sclk/div serial clock/clock divider. serial clock when spen is low. clock divider when spen is high. 47 cs /outsel serial-port select/data output mode. serial-port select when spen is low. data output mode selection when spen is high. ?p exposed pad. internally connected to gnd. connect to a large ground plane to maximize thermal performance. MAX19517 + ? digital error correction flash adc x2 dac stage 2 in_+ in_- stage 1 stage 9 stage 10 end of pipeline d0_ through d9_ figure 1. pipeline architecture?tage blocks
MAX19517 dual-channel, 10-bit, 130msps adc 14 ______________________________________________________________________________________ t/h ina+ cma refio cmb ina- output drivers data and output format pipeline adc pipeline adc clock clock digital error correction internal reference generator reference and bias system digital error correction duty- cycle equalizer clock divider d0a?9a dclkb shdn gnd dorb d0b?9b ovdd (1.8v to 3.3v) avdd (1.8v or 2.5v to 3.3v) dclka dora t/h inb+ inb- clk+ clk- sync cs sclk sdin serial port and control registers internal control 1.8v internal regulator and power control spen MAX19517 MAX19517 c par 0.7pf ina+ *v com *v com programmable from 0.45v to 1.35v. see common-mode register (08h) avdd cma 2k ? 2k ? c sample 1.2pf c sample 1.2pf c par 0.7pf ina- avdd sampling clock r switch 120 ? r switch 120 ? figure 2. functional diagram figure 3. internal track-and-hold (t/h) circuit
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 15 reference input/output (refio) refio adjusts the reference potential, which, in turn, adjusts the full-scale range of the adc. figure 4 shows a simplified schematic of the reference system. an internal bandgap voltage generator provides an internal reference voltage. the bandgap potential is buffered and applied to refio through a 10k ? resistor. bypass refio with a 0.1? capacitor to agnd. the bandgap voltage is applied to a scaling and level-shift circuit, which creates internal reference potentials that estab- lish the full-scale range of the adc. apply an external voltage on refio to trim the adc full scale. the allow- able adjustment range is +5/-15%. the refio-to-adc gain transfer function is: v fs = 1.5 x [v refio /1.25] volts programming and interface there are two ways to control the MAX19517 operating modes. full feature selection is available using the spi interface, while the parallel interface offers a limited set of commonly used features. the programming mode is selected using the spen input. drive spen low for spi interface; drive spen high for parallel interface. parallel interface the parallel interface offers a pin-programmable inter- face with a limited feature set. connect spen to avdd to enable the parallel interface. see table 1 for pin functionality; see figure 5 for a simplified parallel-inter- face input schematic. bandgap reference buffer 1.250v refio internal gain?ypass refio external gain control?rive refio scale and level shift internal reference (controls adc gain) 10k ? 0.1 f external bypass figure 4. simplified reference schematic 36k ? 156k ? cs sclk sdin avdd 29/32 avdd decoder to control logic 23/32 avdd 3/32 avdd figure 5. simplified parallel-interface input schematic spen sdin/format sclk/div cs /outsel description 0 sdin sclk cs spi interface active. features are programmed through the serial port (see the serial programming interface section). 1 0 x x two? complement 1 avdd x x offset binary 1 unconnected x x gray code 1 x 0 x clock divide-by-1 1 x avdd x clock divide-by-2 1 x unconnected x clock divide-by-4 1 x x 0 cmos (dual bus) 1 x x avdd mux cmos (channel a data bus) 1 x x unconnected mux cmos (channel b data bus) table1. parallel-interface pin functionality x = don? care.
MAX19517 dual-channel, 10-bit, 130msps adc 16 ______________________________________________________________________________________ serial programming interface a serial interface programs the MAX19517 control reg- isters through the cs , sdin, and sclk inputs. serial data is shifted into sdin on the rising edge of sclk when cs is low. the MAX19517 ignores the data pre- sented at sdin and sclk when cs is high. c c s s must transition high after each read/write operation . sdin also serves as the serial-data output for reading control registers. the serial interface supports two-byte transfer in a communication cycle. the first byte is a control byte, containing the address and read/write instruction, written to the MAX19517. the second byte is a data byte and can be written to or read from the MAX19517. figure 6 shows a serial-interface communication cycle. the first sdin bit clocked in establishes the communi- cation cycle as either a write or read transaction (0 for write operation and 1 for read operation). the following 7 bits specify the address of the register to be written or read. the final 8 sdin bits are the register data. all address and data bits are clocked in or out msb first. during a read operation, the MAX19517 serial port dri- ves read data (d7) into sdin after the falling edge of sclk following the 8th rising edge of sclk. since the minimum hold time on sdin input is zero, the master can stop driving sdin any time after the 8th rising edge of sclk. subsequent data bits are driven into sdin on the falling edge of sclk. output data in a read opera- tion is latched on the rising edge of sclk. figure 7 shows the detailed serial-interface timing diagram. r/w a6 a4 a5 a2 a3 a0 a1 d7 d6 d4 d5 d2 d3 d0 d1 r/w 0 = write 1 = read cs sclk sdin address data write or read cs t css t csh t sdd t sds t sdh t sclk sclk sdin write read figure 6. serial-interface communication cycle figure 7. serial-interface timing diagram
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 17 bit no. value description 7 0 reserved 6 0 reserved 5 0 or 1 1 = rom read in progress 4 0 or 1 1 = rom read completed and register data is valid (checksum is ok) 3 0 reserved 2 1 reserved 1 0 or 1 reserved 0 0 or 1 1 = duty-cycle equalizer dll is locked table 2. register 0ah status byte address por default function 00h 00000011 power management 01h 00000000 output format 02h 00000000 digital output power management 03h 01101101 data/dclk timing 04h 00000000 c h a d ata outp ut ter m i nati on contr ol 05h 00000000 c h b d ata outp ut ter m i nati on contr ol 06h 00000000 c l ock d i vi d e/d ata for m at/test p atter n 07h reserved reserved?o not use 08h 00000000 common mode 0ah software reset table 3. user-programmable registers register address 0ah is a special-function register. writing data 5ah to register 0ah initiates a register reset. when this operation is executed, all control regis- ters are reset to default values. a read operation of reg- ister 0ah returns a status byte with information described in table 2. the shdn input (pin 7) toggles between any two power-management states. the power management register defines each power-management state. in the default state, shdn = 1 shuts down the MAX19517 and shdn = 0 returns to full power. user-programmable registers power management (00h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hps_shdn1 stby_shdn1 c h b_on _s h d n 1c h a_o n _s h d n 1 hps_shdn0 stby_shdn0 chb_on_shdn0 c h a_o n _s h d n 0
MAX19517 dual-channel, 10-bit, 130msps adc 18 ______________________________________________________________________________________ hps_shdn0 stby_shdn0 cha_on_shdn0 chb_on_shdn0 shdn input = 0* hps_shdn1 stby_shdn1 cha_on_shdn1 chb_on_shdn1 shdn input = 1** x 0 0 0 complete power-down 0 0 0 1 channel b active, channel a full power-down 0 0 1 0 channel a active, channel b full power-down 0 x 1 1 channels a and b active 0 1 0 0 channels a and b in standby mode 0 1 0 1 channel b active, channel a standby 0 1 1 0 channel a active, channel b standby 1 1 0 0 channels a and b in standby mode 1 x 1 x channels a and b active, output is averaged 1 x x 1 channels a and b active, output is averaged control bits: output format (01h) in addition to power management, the hps_shdn1 and hps_shdn0 activate an a+b adder mode. in this mode, the results from both channels are averaged. the mux_ch bit selects which bus the (a+b)/2 data is presented. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 bit_order_b bit_order_a mux_ch mux 0 * hps_shdn0, stby_shdn0, cha_on_shdn0, and chb_on_shdn0 are active when shdn = 0. ** hps_shdn1, stby_shdn1, cha_on_shdn1, and chb_on_shdn1 are active when shdn = 1. x = don? care. note: when hps_shdn_ = 1 (a+b adder mode), cha_on and chb_on must both equal 0 for power-down or standby. bit 7, 6, 5 set to 0 for proper operation bit 4 bit_order_b: reverse chb output bit order 0 = defined data bus pin order (default) 1 = reverse data bus pin order bit 3 bit_order_a: reverse cha output bit order 0 = defined data bus pin order (default) 1 = reverse data bus pin order bit 2 mux_ch: multiplexed data bus selection 0 = multiplexed data output on cha (cha data presented first, followed by chb data) (default) 1 = multiplexed data output on chb (chb data presented first, followed by cha data) bit 1 mux: digital output mode 0 = dual data bus output mode (default) 1 = single multiplexed data bus output mode mux_ch selects the output bus bit 0 set to 0 for proper operation
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 19 digital output power management (02h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x pd_dout_1 pd_dout_0 dis_dor dis_dclk bit 7? don? care bit 3, 2 pd_dout_1, pd_dout_0: power-down digital output state control 00 = digital output three state (default) 01 = digital output low 10 = digital output three state 11 = digital output high bit 1 dis_dor: dor driver disable 0 = dor active (default) 1 = dor disabled (three state) bit 0 dis_dclk: dclk driver disable 0 = dclk active (default) 1 = dclk disabled (three state)
MAX19517 dual-channel, 10-bit, 130msps adc 20 ______________________________________________________________________________________ data/dclk timing (03h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 da_bypass dly_half_t dclktime_2 dclktime_1 dclktime_0 dtime_2 dtime_1 dtime_0 bit 7 da_bypass: data aligner bypass 0 = nominal (default) 1 = bypasses data aligner delay line to minimize output data latency with respect to the input clock. rising clock to data transition is approximately 6ns with dtime = 000b settings bit 6 dly_half_t: data and dclk delayed by t/2 0 = normal, no delay 1 = delays data and dclk outputs by t/2 (default) disabled in mux data bus mode bit 5, 4, 3 dclktime_2, dclktime_1, dclktime_0: dclk timing adjust (controls both channels) 000 = nominal 001 = +t/16 010 = +2t/16 011 = +3t/16 100 = reserved, do not use 101 = -1t/16 (default) 110 = -2t/16 111 = -3t/16 bit 2, 1, 0 dtime_2, dtime_1, dtime_0: data timing adjust (controls both channels) 000 = nominal 001 = +t/16 010 = +2t/16 011 = +3t/16 100 = reserved, do not use 101 = -1t/16 (default) 110 = -2t/16 111 = -3t/16
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 21 cha data output termination control (04h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x ct_dclk_2_a ct_dclk_1_a ct_dclk_0_a ct_data_2_a ct_data_1_a ct_data_0_a bit 7, 6 don? care bit 5, 4, 3 ct_dclk_2_a, ct_dclk_1_a, ct_dclk_0_a: cha dclk termination control 000 = 50 ? (default) 001 = 75 ? 010 = 100 ? 011 = 150 ? 1xx = 300 ? bit 2, 1, 0 ct_data_2_a, ct_data_1_a, ct_data_0_a: cha data output termination control 000 = 50 ? (default) 001 = 75 ? 010 = 100 ? 011 = 150 ? 1xx = 300 ? chb data output termination control (05h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x ct_dclk_2_b ct_dclk_1_b ct_dclk_0_b ct_data_2_b ct_data_1_b ct_data_0_b bit 7, 6 don? care bit 5, 4, 3 ct_dclk_2_b, ct_dclk_1_b, ct_dclk_0_b: chb dclk termination control 000 = 50 ? (default) 001 = 75 ? 010 = 100 ? 011 = 150 ? 1xx = 300 ? bit 2, 1, 0 ct_data_2_b, ct_data_1_b, ct_data_0_b: chb data output termination control 000 = 50 ? (default) 001 = 75 ? 010 = 100 ? 011 = 150 ? 1xx = 300 ?
MAX19517 dual-channel, 10-bit, 130msps adc 22 ______________________________________________________________________________________ clock divide/data format/test pattern (06h) reserved (07h)?o not write to this register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test_pattern test_data format_1 format_0 term_100 sync_mode div1 div0 bit 7 test_pattern: test pattern selection 0 = ramps from 0 to 1023 (offset binary) and repeats (subsequent formatting applied) (default) 1 = data alternates between d[9:0] = 0101010101, dor = 1, and d[9:0] = 1010101010, dor = 0 on both channels bit 6 test_data: data test mode 0 = normal data output (default) 1 = outputs test data pattern bit 5, 4 format_1, format_0: data numerical format 00 = two? complement (default) 01 = offset binary 10 = gray code 11 = two? complement bit 3 term_100: select 100 ? clock input termination 0 = no termination (default) 1 = 100 ? termination across differential clock inputs bit 2 sync_mode: divider synchronization mode select 0 = slip mode (figure 11) (default) 1 = edge mode (figure 12) bit 1, 0 div1, div0: input clock-divider select 00 = no divider (default) 01 = divide-by-2 10 = divide-by-4 11 = no divider
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 23 common mode (08h) software reset (0ah) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmi_self_b cmi_adj_2_b cmi_adj_1_b cmi_adj_0_b cmi_self_a cmi_adj_2_a cmi_adj_1_a cmi_adj_0_a bit 7 cmi_self_b: chb connect input common-mode to analog inputs 0 = internal common-mode voltage is not applied to inputs (default) 1 = internal common-mode voltage applied to analog inputs through 2k ? resistors bit 6, 5, 4 cmi_adj_2_b, cmi_adj_1_b, cmi_adj_0_b: chb input common-mode voltage adjustment 000 = 0.900v (default) 001 = 1.050v 010 = 1.200v 011 = 1.350v 100 = 0.900v 101 = 0.750v 110 = 0.600v 111 = 0.450v bit 3 cmi_self_a: cha connect input common-mode to analog inputs 0 = internal common-mode voltage is not applied to inputs (default) 1 = internal common-mode voltage applied to analog inputs through 2k ? resistors bit 2, 1, 0 cmi_adj_2_a, cmi_adj_1_a, cmi_adj_0_a: cha input common-mode adjustment 000 = 0.900v (default) 001 = 1.050v 010 = 1.200v 011 = 1.350v 100 = 0.900v 101 = 0.750v 110 = 0.600v 111 = 0.450v bit 7? swreset: write 5ah to initiate software reset
clock inputs the input clock interface provides for flexibility in the requirements of the clock driver. the MAX19517 accepts a fully differential clock or single-ended logic-level clock. for differential clock operation, connect a differential clock to the clk+ and clk- inputs. in this mode, the input common mode is established internally to allow for ac-coupling. the differential clock signal can also be dc-coupled if the common mode is constrained to the specified 1v to 1.4v clock input common-mode range. for single-ended operation, connect clk- to gnd and drive the clk+ input with a logic-level signal. when the clk- input is grounded (or pulled below the threshold of the clock mode detection comparator) the differential-to- single-ended conversion stage is disabled and the logic- level inverter path is activated. clock divider the MAX19517 offers a clock-divider option. enable clock division either by setting div0 and div1 through the serial interface; see the clock divide/data MAX19517 dual-channel, 10-bit, 130msps adc 24 ______________________________________________________________________________________ clk+ 100 ? termination (programmable) self-bias turned off for single-ended clock or power-down. clk- gnd avdd 10k ? 20k ? 5k ? 5k ? 50 ? 50 ? 2:1 mux select threshold figure 8. simplified clock input schematic dclk data, dor sample clock n n+1 sample on rising edge n+2 n+4 n+5 n-9 n-8 n-10 n-7 n-6 n-5 n-4 t clk t setup t ch t dd t dc t hold t cl dual-bus output mode sample clock is the derived clock from (clk+ - clk-)/clock divider, in_ = in_+ - in_-. sampling instant sampling instant sampling instant sampling instant sampling instant sampling instant in_ t ad n+3 figure 9. dual-bus output mode timing
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 25 format/test pattern register (06h) for clock-divider options, or in parallel programming configuration ( spen = 1) by using the div input. system timing requirements figures 9 and 10 depict the relationship between the clock input and output, analog input, sampling event, and data output. the MAX19517 samples on the rising edge of the sampling clock. output data is valid on the next rising edge of dclk after a nine-clock internal latency. for applications where the clock is divided, the sample clock is the divided internal clock derived from: [(clk+ - clk-)/divider] synchronization when using the clock divider, the phase of the internal clock can be different than that of the fpga, microcon- troller, or other MAX19517s in the system. there are two mechanisms to synchronize the internal clock: slip synchronization and edge synchronization. select the synchronization mode using sync_mode (bit 2) in the clock divide/data format/test pattern register (06h) and drive the syncin input high to synchronize. slip synchronization mode, sync_mode = 0 (default): on the third rising edge of the input clock (clk) after the rising edge of sync (provided set-up and hold times are met), the divided output is forced to skip a state transition (figure 11). edge synchronization mode, sync_mode = 1: on the third rising edge of the input clock (clk) after the rising edge of sync (provided set-up and hold times are met), the divided output is forced to state 0. a divid- ed clock rising edge occurs on the fourth (/2 mode) or fifth (/4 mode) rising edge of clk, after a valid rising edge of sync (figure 12). dclk data, dor sample clock n-9 cha chb n-9 n-8 cha chb n-8 chb n-10 n-7 cha chb n-7 n-6 cha chb n-6 n-5 cha chb n-5 n-4 cha chb n-4 mux output mode in_ sampling instant sampling instant sampling instant sampling instant sampling instant sampling instant t ad n n+1 n+2 n+4 n+5 n+3 t ch t cl sample on rising edge t dc t dd t cha t dch t setup t hold t hold t dcl t setup t chb sample clock is the derived clock from (clk+ - clk-)/clock divider, in_ = in_+ - in_-. mux_ch (bit 2, output format 01h) determines the output bus and which channel data is presented. t clk figure 10. multiplexed output mode timing
MAX19517 dual-channel, 10-bit, 130msps adc 26 ______________________________________________________________________________________ syncin syncin 2x input clk 4x input clk 1x divided clk (state) 1x divided clk (state) t suv = set-up time for valid clock edge. t ho = hold-off time for invalid clock edge. divide-by-2 slip syncronization 1234 1234 slip slip (1) (0) (1) (0) (1) (0) (1) (1) (0) (1) (0) (1) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (0) (0) divide-by-4 slip synchronization 5 (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (3) (0) (1) (2) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) t ho t suv t ho t suv figure 11. slip synchronization mode
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 27 syncin syncin 2x input clk 4x input clk 1x divided clk (state) 1x divided clk (state) t suv = set-up time for valid clock edge. t ho = hold-off time for invalid clock edge. divide-by-2 edge syncronization t ho t suv t ho t suv 1234 1234 (1) (0) (1) (0) (1) (0) (1) (0) (1) (1) (0) (1) (0) force to 0 force to 0 (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (0) divide-by-4 edge synchronization 5 (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (1) (2) (3) (0) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (3) (0) (1) (2) figure 12. edge synchronization mode
MAX19517 dual-channel, 10-bit, 130msps adc 28 ______________________________________________________________________________________ digital outputs the MAX19517 features a dual cmos, multiplexable, reversible data bus. in parallel programming mode, con- figure the data outputs (d0_?9_) for offset binary, two? complement, or gray code using the format input. select multiplexed or dual-bus operation using the out- sel input. see the output format register (01h) for details on output formatting using the spi interface. the spi interface offers additional flexibility where d0_?9_ are reversed, so the lsb appears at d9_ and the msb at d0_. ovdd sets the output voltage; set ovdd between 1.8v and 3.3v. the digital outputs feature programmable output impedance from 50 ? to 300 ? . set the output impedance for each bus using the ch_ data output termination control registers (04h and 05h). programmable data timing the MAX19517 provides programmable data timing con- trol to allow for optimization of timing characteristics to meet the system timing requirements. the timing adjust- ment feature also allows for adc performance improve- ments by shifting the data output transition away from the sampling instant. the data timing control signals are summarized in table 4. the default settings for timing adjustment controls are given in table 5. many applica- tions will not require adjustment from the default settings. the effects of the data timing adjustment settings are illustrated in figures 13 and 14. the x axis is sampling rate and the y axis is data delay in units of clock period. the solid lines are the nominal data timing characteris- tics for the 14 available states of dtime and dly_half_t. the heavy line represents the nominal data timing characteristics for the default settings. note that the default timing adjustment setting for the MAX19517 130msps adc results in an additional period of data latency. tables 6 and 7 show the recommended timing control settings versus sampling rate. the nominal data timing characteristics versus sampling rate for these recommended timing adjustment settings are shown in figures 15 and 16. when da_bypass = 1, the dclktime delay setting must be equal to or less than the dtime delay setting, as shown in table 8. power management the shdn input (pin 7) toggles between any two power- management states. the power management register (00h) defines each power-management state. in default state, shdn = 1 shuts down the MAX19517 and shdn = 0 returns to full power. use of the shdn input is not required for power management. for either state of shdn, complete power-management flexibility is provid- ed, including individual adc channel power-manage- ment control, through the power management register (00h). the available reduced-power modes are shut- down and standby. in standby mode, the reference and duty-cycle equalizer circuits remain active for rapid wake-up time. in standby mode, the externally applied clock signal must remain active for the duty-cycle equal- izer to remain locked. typical wake-up time from standby mode is 15?. in shutdown mode, all circuits are turned off except for the reference circuit required for the inte- grated self-sensing voltage regulator. if the regulator is active, there is additional supply current associated with the regulator circuit when the device is in shutdown. typical wake-up time from shutdown mode is 5ms, which is dominated by the rc time constant on refio. data timing control description da_bypass data aligner bypass. when this control is active (high), data and dclk delay is reduced by approximately 2.6ns (relative to da_bypass = 0). dly_half_t when this control is active, data output is delayed by half clock period (t/2). this control does not delay data output if mux mode is active. dtime<2:0> allows adjustment of data output delay in t/16 increments, where t is the sample clock period. dclktime<2:0> provides adjustment of dclk delay in t/16 increments, where t is the sample clock period. when dtime and dclktime are adjusted to the same setting, the rising edge of dclk occurs t/8 prior to data transitions. table 4. data timing controls data timing control default description da_bypass 0 data aligner active dly_half_t 1 t/2 delay (3.85ns at 130msps) dtime<2:0> 101 -t/16 (0.48ns at 130msps) dclktime<2:0> 101 -t/16 (0.48ns at 130msps) table 5. data timing control default settings
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 29 figure 15. recommended data timing (v ovdd = 1.8v) recommended data timing vs. sampling rate sampling rate (msps) data delay (t fractional period) 125 115 105 95 85 75 0.5 1.0 1.5 2.0 0 65 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +5/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 ovdd = 1.8v da_bypass = 1 figure 16. recommended data timing (v ovdd = 3.3v) recommended data timing vs. sampling rate sampling rate (msps) data delay (t fractional period) 125 115 105 95 85 75 0.5 1.0 1.5 2.0 0 65 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +5/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 ovdd = 3.3v da_bypass = 1 sampling rate (msps) v ovdd = 1.8v from to da_bypass dly_half_t dtime<2:0> dclktime<2:0> 65 75 1 0 111 111 75 86 1 1 011 011 86 96 1 1 010 010 96 106 1 1 001 001 106 116 1 1 000 000 116 130 1 1 101 101 table 6. recommended timing adjustments (v ovdd = 1.8v) figure 13. default data timing (v ovdd = 1.8v) factory default nominal data timing vs. sampling rate sampling rate (msps) data delay (t fractional period) 125 115 105 95 85 75 0.5 1.0 1.5 2.0 0 65 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +5/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 ovdd = 1.8v da_bypass = 0 figure 14. default data timing (v ovdd = 3.3v) factory default nominal data timing vs. sampling rate sampling rate (msps) data delay (t fractional period) 125 115 105 95 85 75 0.5 1.0 1.5 2.0 0 65 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +5/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 ovdd = 3.3v da_bypass = 0
MAX19517 dual-channel, 10-bit, 130msps adc 30 ______________________________________________________________________________________ integrated voltage regulator the MAX19517 includes an integrated self-sensing lin- ear voltage regulator on the analog supply (avdd). see figure 17. when the applied voltage on avdd is below 2v, the voltage regulator is bypassed, and the core analog circuitry operates from the externally applied voltage. if the applied voltage on avdd is higher than 2v, the regulator bypass switches off, and voltage reg- ulator mode is enabled. when in voltage regulation mode, the internal-core analog circuitry operates from a stable 1.8v supply voltage provided by the regulator. the regulator provides an output voltage of 1.8v over a 2.3v to 3.5v avdd input-voltage range. since the power-supply current is constant over this voltage range, analog power dissipation is proportional to the applied voltage. power-on and reset the user-programmable register default settings and other factory-programmed settings are stored in non- volatile memory. upon device power-up, these values are loaded into the control registers. this operation occurs after application of supply voltage to avdd and applica- tion of an input clock signal. the register values are retained as long as avdd is applied. while avdd is applied, the registers can be reset, which will overwrite all user-programmed registers with the default values. this reset operation can be initiated by software command through the serial-port interface or by hardware control using the spen and shdn inputs. the reset time is pro- portional to the adc clock period and requires 65? at 130msps. table 9 summarizes the reset methods. sampling rate (msps) v ovdd = 3.3v from to da_bypass dly_half_t dtime<2:0> dclktime<2:0> 65 77 1 0 101 101 77 91 1 0 110 110 91 102 1 0 111 111 102 120 1 1 011 011 120 130 1 1 010 010 table 7. recommended timing adjustments (v ovdd = 3.3v) dtime<2:0> allowed dclktime<2:0> settings 111 (-3t/16) 111 (-3t/16) 110 (-2t/16) 110 (-2t/16); 111 (-3t/16) 101 (-1t/16) 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 000 (nominal) 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 001 (+1t/16) 001 (+1t/16); 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 010 (+2t/16) 010 (+2t/16); 001 (+1t/16); 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 011 (+3t/16) 011 (+3t/16); 010 (+2t/16); 001 (+1t/16); 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) table 8. allowed settings of dclktime and dtime for da_bypass = 1 reset mode description power-on reset upon power-up (avdd supply voltage and clock signal applied), the por (power-on-reset) circuit initiates a register reset. software reset write data 5ah to address 0ah to initiate register reset. hardware reset a register reset is initiated by the falling edge on the shdn pin when spen is high. table 9. reset methods
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 31 applications information analog inputs transformer-coupled differential analog input the MAX19517 provides better sfdr and thd with fully differential input signals than a single-ended input drive. in differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the adc inputs only require half the signal swing compared to single-ended input mode. an rf transformer (figure 18) provides an excellent solution for converting a single-ended signal to a fully differential signal. connecting the center tap of the transformer to cm_ provides a common-mode voltage. the transformer shown has an impedance ratio of 1:1.4. alternatively, a different step-up transformer can be selected to reduce the drive requirements. a reduced signal swing from the input driver can also improve the overall distortion. the configuration of figure 18 is good for frequencies up to nyquist (f clk /2). figure 17. integrated voltage regulator in 2.3v to 3.5v enable out 1.8v regulator reference internal analog circuits avdd (pins 1, 12, 13, 48) gnd figure 19. transformer-coupled input drive for input frequencies beyond nyquist 1 5 3 6 2 4 n.c. v in 0.1 f t1 mini-circuits adt1-1wt in_+ cm_ in_- n.c. 1 5 3 6 2 4 n.c. t2 mini-circuits adt1-1wt n.c. 75 ? 0.5% 75 ? 0.5% 110 ? 0.5% 110 ? 0.5% 0.1 f MAX19517 figure 18. transformer-coupled input drive for input frequencies up to nyquist MAX19517 1 5 3 6 2 4 n.c. n.c. v in 0.1 f t1 mini-circuits adt1-1wt 36.5 ? 0.5% 36.5 ? 0.5% 0.1 f in_+ cm_ in_-
MAX19517 dual-channel, 10-bit, 130msps adc 32 ______________________________________________________________________________________ the circuit of figure 19 also converts a single-ended input signal to a fully differential signal. figure 19 uti- lizes an additional transformer to improve the common- mode rejection allowing high-frequency signals beyond the nyquist frequency. a set of 75 ? and 110 ? termina- tion resistors provide an equivalent 50 ? termination to the signal source. the second set of termination resis- tors connect to cm_ providing the correct input com- mon-mode voltage. single-ended ac-coupled input signal figure 20 shows a single-ended, ac-coupled input application. the max4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. bias voltage is applied to the inputs through internal 2k ? resistors. see common mode register 08h for further details. dc-coupled input the MAX19517? wide common-mode voltage range (0.4v to 1.4v) allows dc-coupled signals. ensure that the common-mode voltage remains between 0.4v and 1.4v. clock input figure 21 shows a single-ended-to-differential clock input converting circuit. grounding, bypassing, and board-layout considerations the MAX19517 requires high-speed board-layout design techniques. locate all bypass capacitors as close as possible to the device, preferably on the same side as the adc, using surface-mount devices for mini- mum inductance. bypass avdd, ovdd, refio, cma, and cmb with 0.1? ceramic capacitors to gnd. multilayer boards with ground and power planes pro- duce the highest level of signal integrity. route high- speed digital signal traces away from the sensitive ana- log traces of either channel. make sure to isolate the analog input lines to each respective converter to mini- mize channel-to-channel crosstalk. keep all signal lines short and free of 90 turns. definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a best-fit straight line. worst-case deviation is defined as inl. differential nonlinearity (dnl) dnl is the difference between the measured transfer function step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. dnl deviations are measured at each step of the transfer function and the worst-case deviation is defined as dnl. offset error offset error is a parameter that indicates how well the actual transfer function matches the ideal transfer func- tion at midscale. ideally, the midscale transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. gain error gain error is a figure of merit that indicates how well the slope of the measured transfer function matches the slope of the ideal transfer function based on the speci- fied full-scale input-voltage range. the gain error is defined as the relative error of the measured transfer function and is expressed as a percentage. figure 20. single-ended, ac-coupled input drive MAX19517 0.1 f 100 ? 100 ? 0.1 f in_+ cm_ 0.1 f in_- max4108 v in figure 21. single-ended-to-differential clock input MAX19517 49.9 ? 49.9 ? 0.01 f 0.1 f 0.01 f clk+ clk- clkin
MAX19517 dual-channel, 10-bit, 130msps adc ______________________________________________________________________________________ 33 small-signal noise floor (ssnf) ssnf is the integrated noise and distortion power in the nyquist band for small-signal inputs. the dc offset is excluded from this noise calculation. for this converter, a small signal is defined as a single tone with an amplitude less than -35dbfs. this parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise fig- ure of a receive channel. refer to www.maxim-ic.com for application notes on thermal + quantization noise floor. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr [max] = 6.02 x n + 1.76 in reality, there are other noise sources besides quanti- zation noise (e.g., thermal noise, reference noise, clock jitter, etc.). snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist frequency exclud- ing the fundamental, the first six harmonics (hd2?d7), and the dc offset. signal-to-noise and distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise plus the rms distortion. rms noise includes all spectral components to the nyquist frequency excluding the fundamental, the first six har- monics (hd2?d7), and the dc offset. rms distortion includes the first six harmonics (hd2?d7). single-tone spurious-free dynamic range (sfdr1 and sfdr2) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms amplitude of the next largest spurious component, excluding dc offset. sfdr1 reflects the spurious performance based on worst 2nd-order or 3rd-order harmonic distortion. sfdr2 is defined by the worst spurious component excluding 2nd- and 3rd- order harmonics and dc offset. total harmonic distortion (thd) thd is the ratio of the rms of the first six harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 ? 7 are the amplitudes of the 2nd-order through 7th-order har- monics (hd2?d7). third-order intermodulation (im3) im3 is the total power of the third-order intermodulation products to the nyquist frequency relative to the total input power of the two input tones f in1 and f in2 . the individual input tone levels are at -7dbfs. the third- order intermodulation products are: 2 x f in1 - f in2 , 2 x f in2 - f in1 , 2 x f in1 + f in2 , 2 x f in2 + f in1 . aperture delay the input signal is sampled on the rising edge of the sampling clock. there is a small delay between the ris- ing edge of the sampling clock and the actual sampling instant, which is defined as aperture delay (t ad ). aperture jitter aperture jitter (t aj ) is defined as the sample-to-sample time variation in the aperture delay. overdrive recovery time overdrive recovery time is the time required for the adc to recover from an input transient that exceeds the full-scale limits. the specified overdrive recovery time is measured with an input transient that exceeds the full- scale limits by ?0%. process information process: cmos thd vvvvvv v log = +++++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 7 2 1 sinad noise distortion signal rms rms rms log = + ? ? ? ? ? ? ? ? 20 22 snr signal noise rms rms log = ? ? ? ? ? ? 20
MAX19517 dual-channel, 10-bit, 130msps adc 34 ______________________________________________________________________________________ package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 48 tqfn-ep t4877-4 21-0144 top view MAX19517 13 14 15 16 17 18 19 20 21 22 23 24 avdd sync clk+ clk- gnd gnd dorb dclkb d0b d1b d2b d3b 48 47 46 45 44 43 42 41 40 39 38 37 1 2 345678910 11 12 avdd cs/outsel sclk/div sdin/format dclka dora d9a d8a d7a d6a d5a d4a avdd cmb inb- inb+ i.c. shdn refio spen ina- ina+ cma avdd 36 35 34 33 32 31 30 29 28 27 26 25 ovdd d4b d5b d6b d7b d8b d9b d0a d1a d2a d3a ovdd + *ep *exposed pad pin configuration
MAX19517 dual-channel, 10-bit, 130msps adc maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 35 ? 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/08 initial release ? 1 10/08 corrected error in vertical scale for toc 32 11

▲Up To Search▲

Price & Availability of MAX19517

	To Download MAX19517 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .